Example embodiments of inventive concepts relate to a method of designing a semiconductor device, and more particularly, to a method of designing a semiconductor device, which physically implements a power-gating circuit to which super cut-off and multi-fanout technology are applied.
A semiconductor device may be manufactured by patterning devices and mutual connections thereof on a substrate such as a semiconductor wafer. A semiconductor device may be manufactured through a process in which a designer designs an integrated circuit using electronic design automation (hereinafter referred to as “EDA”), which enables various circuit components to be placed to interact with each other and to be connected to each other. In other words, a layout designer may generate the layout of a semiconductor device using EDA.
The layout of a semiconductor device includes the physical locations and sizes of circuit components, connection wires, and various layers. The layout of a semiconductor device may be verified and transferred to a semiconductor substrate, and thus the semiconductor device may be manufactured.
In order to reduce the power consumption of such a semiconductor device, for example, a system-on-chip (hereinafter referred to as “SoC”), a power-gating circuit is used.
Further, in order to reduce leakage current that may occur in a power cut-off switch even in a sleep mode, technology for supplying a memory voltage having a relatively stable and high value to a PMOS transistor that forms a power cut-off switch has been proposed. This technology is hereinafter referred to as “super cut-off technology”.
Furthermore, a semiconductor device having a multi-fanout structure, in which a single control circuit controls a plurality of header cells, has been proposed so as to reduce and/or minimize leakage current and effectively use physical resources.
However, as the size of semiconductor devices has become smaller, in a semiconductor device to which the above-described multi-fanout and super cut-off technology are applied, limiting and/or preventing a max transition time violation (MTTV) problem, wiring congestion problem, and a gate oxide breakdown caused by an antenna effect may be an issue.